Communication and synchronization between master controller and coprocessors are critical issues in the design of parallel system-on-chip architectures, especially when applications are developed in a high-level programming language and run on a virtual run-time environment (such as a Java Virtual Machine). In this paper we propose a design space exploration environment based on a general HW-SW architectural template and a full-system cycle-accurate simulation tool, built on top of Simics. Our flow takes accurately into account the overheads caused by operating system, virtual environment, drivers, synchronization mechanisms and non-ideal memory system. In a top-down co-design flow, the proposed approach bridges the abstraction gap between HW-SW partitioning and HW synthesis. In particular it provides: i) a realistic evaluation of the effectiveness of a tentative partitioning, ii) guidelines for designing the HW-SW interface, iii) performance constraints for the synthesis of the HW components.

Exploring Coprocessor Interfaces in an Embedded Java Environment

LATTANZI, EMANUELE;BOGLIOLO, ALESSANDRO
2003-01-01

Abstract

Communication and synchronization between master controller and coprocessors are critical issues in the design of parallel system-on-chip architectures, especially when applications are developed in a high-level programming language and run on a virtual run-time environment (such as a Java Virtual Machine). In this paper we propose a design space exploration environment based on a general HW-SW architectural template and a full-system cycle-accurate simulation tool, built on top of Simics. Our flow takes accurately into account the overheads caused by operating system, virtual environment, drivers, synchronization mechanisms and non-ideal memory system. In a top-down co-design flow, the proposed approach bridges the abstraction gap between HW-SW partitioning and HW synthesis. In particular it provides: i) a realistic evaluation of the effectiveness of a tentative partitioning, ii) guidelines for designing the HW-SW interface, iii) performance constraints for the synthesis of the HW components.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11576/1879280
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